ddu12h 5-tap, ecl-interfaced fixed delay line (series ddu12h) features packages ? ten equally spaced outputs ? fits in 300 mil 32-pin dip socket ? input & outputs fully 10kh-ecl interfaced & buffered functional description d a ta delay devices, i n c. ? 3 32 31 30 29 24 23 22 21 1 3 4 5 8 9 11 12 16 gn d t2 t4 in vee gn d t2 t4 vee gn d t1 t3 t5 gn d t6 t8 t10 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 gn d t2 t4 in n/c vee gn d n/c n/c t7 t8 vee gn d t1 t3 t5 n/c n/c gn d n/c n/c t6 t8 t1 0 ddu1 2 h - x x d i p d d u 1 2 h - x x m m ilita r y d i p d d u 12h -x x c 4 sm d ddu1 2 h -x x m c4 m i l sm d the ddu12h-series device is a 10-tap digitally buffered delay line. the signal input (in) is reproduced at the outputs (t1-t10), shifted in time by an amount determined by the device das h number (see table). for dash numbers less than 20, the total delay of the line is measured from t1 to t10. the nominal tap-to-tap delay in crement is given by one-ninth of the total delay, and the inherent delay from in to t1 is nominally 1.5ns. for dash numbers greater than or equal to 20, the total delay of the line is measured from in to t10. the nominal tap-to-tap delay increment is given by one-tenth of this number. pin descriptions in signal input t1-t10 tap outputs vee -5 volts gnd ground series specifications dash number specifications part number total delay (ns) delay per tap (ns) ddu12h-10 9 1.0 * 1.0 0.3 ddu12h-20 20 2.0 2.0 0.4 ddu12h-25 25 2.0 2.5 0.4 ddu12h-40 40 2.0 4.0 0.5 ddu12h-50 50 2.5 5.0 1.0 ddu12h-75 75 4.0 7.5 1.5 ddu12h-100 100 5.0 10.0 2.0 ddu12h-150 150 7.5 15.0 2.0 ddu12h-200 200 10.0 20.0 2.0 ddu12h-250 250 12.5 25.0 2.0 ddu12h-300 300 15.0 30.0 2.0 ddu12h-400 400 20.0 40.0 2.0 ddu12h-500 500 25.0 50.0 2.5 ddu12h-750 750 37.5 75.0 4.0 ddu12h-1000 1000 50.0 100.0 5.0 ddu12h-1500 1500 75.0 150.0 7.0 * total delay is referenced to first tap output input to first tap = 1.5ns 1ns note: a n y dash number betw een 10 and 1500 not show n is also av ailable. ? minimum input pulse w i dth: 10% of total delay ? output rise time: 2ns typical ? supply v o ltage: -5vdc 5% ? pow e r dissipation: 400mw typical (no load) ? operating temperature: -30 to 85 c ? tem p . coefficient of total delay : 100 ppm/ c 10 % 10 % 10 % 10 % vc c gn d i n t 1 t2 t3 t4 t 1 0 f uncti onal d i ag ram fo r dash nu m b ers < 20 1. 5ns 10 % 10 % 10 % 10 % t5 t6 t7 t8 10 % t9 10 % 10 % 10 % 10 % vc c gn d i n t 1 t2 t3 t4 t 1 0 f uncti onal d i ag ram fo r dash nu m b ers >= 20 10 % 10 % 10 % 10 % t5 t6 t7 t8 10 % t9 10 % ? 1997 data delay dev i ces doc #97036 data delay devices, inc. 1 5/3/2006 3 mt. prospect ave. clifton, nj 07013
ddu12h application notes high frequency response the ddu12h tolerances are guaranteed for input pulse widths and periods greater than those specified in the test conditions. although the device will function properly for pulse widths as small as 10% of the total delay and periods as small as 20% of the total delay (for a symmetric input), the delays may deviate from their values at low frequency. however, for a given input condition, the deviation will be repeatable from pulse to pulse. contact technical support at data delay devices if your application requires device testing at a specific input condition. power supply bypassing the ddu12h relies on a stable power supply to produce repeatable delays within the stated tolerances. a 0.1uf capac itor from vee to gnd, loc a ted as c l os e as pos s i ble to the vee pin, is recommended. a wide vee trace and a clean ground plane should be used. device specifications table 1: absolute maximum ratings p a r a m e t e r s y m b o l m i n m a x u n i t s n o t e s dc supply voltage v ee - 7 . 0 0 . 3 v input pin voltage v in v ee - 0.3 0.3 v storage temperature t st rg - 5 5 1 5 0 c lead temperature t lead 3 0 0 c 1 0 s e c table 2: dc electrical characteristics (0c to 75c) p a r a m e t e r s y m b o l m i n t y p m a x u n i t s n o t e s high level output voltage v oh - 1 . 0 2 0 - 0 . 7 3 5 v v ih = max,50 ? to -2v low level output voltage v ol - 1 . 9 5 0 - 1 . 6 0 0 v v il = mi n, 50 ? to -2v high level input voltage v ih - 1 . 0 7 0 v low level input voltage v il - 1 . 4 8 0 v high level input current i ih 4 7 5 a v ih = max low level input current i il 0 . 5 a v il = mi n doc #97036 data delay devices, inc. 2 5/3/2006 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com
ddu12h package dimensions ddu12h-xx (co m m e r c ial di p ) ddu12h-xxm (m ilitar y di p ) . 150 . 030 1. 650 t y p . 1 345 8 1 6 12 11 9 . 320 ma x . . 018 ty p . . 400 ty p . . 300 ty p . . 012 t y p . . 020 ty p . 29 30 31 32 21 22 23 24 . 100 . 200 . 300 . 400 . 700 . 800 . 900 1. 000 1. 100 1. 500 . 075 d d u 12h - xxc 4 ( c ommercial sm d ) ddu12h- xxm c4 ( m ilit ary sm d) 1. 280 . 020 . 882 .0 0 . 020 ty p . . 040 ty p . . 100 . 090 1. 100 . 320 ma x . . 590 ma x . . 010 . 002 . 050 .0 1 . 710 .0 0 . 007 .0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 doc #97036 data delay devices, inc. 3 5/3/2006 3 mt. prospect ave. clifton, nj 07013
ddu12h delay line automated testing test conditions input: output: ambient temperature: 25 o c 3 o c load: 50 ? to -2v supply voltage (vcc): -5.0v 0.1v c load : 5pf 10% input pulse: standard 10kh ecl threshold: (v oh + v ol ) / 2 levels (rising & falling) source impedance: 50 ? max. rise/fall time: 2.0 ns max. (measured between 20% and 80%) pulse width: pw in = 1.5 x total delay period: per in = 10 x total delay note: the above conditions are for test only and do not in any way restrict the operation of the device. t1 out tr i g in re f tr i g t est s e t u p de v i ce unde r t est (d u t ) os ci l l o s c op e pu l s e ge ne ra t o r in t2 t3 t4 t5 t6 t7 t8 t9 t1 0 t i mi n g di ag ram f o r t est i n g t ris e t fa l l per in pw in t ris e t fa l l 20% 20% 50% 50% 80% 80% 50% 50% v ih v il v oh v ol in p u t s ign a l ou tp u t s ign a l doc #97036 data delay devices, inc. 4 5/3/2006 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com
|
